Erasable programmable non-volatile memory
US11049564B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.