On chip block repair scheme
US11049585B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Mar 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Field configurable bad block repair for a memory array comprising a plurality of blocks utilizes a block repair information store for data identifying one or more bad blocks in the array. The block repair information store includes nonvolatile memory writable at least once. Block repair circuitry on the device is configurable to redirect commands to access bad blocks identified in the bad block repair information store to reserved blocks in the memory array. A controller is responsive to a command to write bad block repair information, such as an identifier of a bad block in the plurality of blocks to the block repair information store in the field, and to reconfigure the block repair circuitry in the field using the updated information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.