Shuo-Nan Hung
55Patents
6h-index
34Co-inventors
72Inventor score
Filing activity: May 1, 2000 → Sep 14, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8724390B2 | Architecture for a 3D memory array | Physics | 18 | Active |
| US9690650B2 | Storage scheme for built-in ECC operations | Physics | 15 | Active |
| US9136006B2 | Method and device for reducing coupling noise during read operation | Physics | 11 | Active |
| US8760928B2 | NAND flash biasing operation | Physics | 9 | Active |
| US10957384B1 | Page buffer structure and fast continuous read | Physics | 7 | Active |
| US9165680B2 | Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks | Physics | 6 | Active |
| US8587998B2 | 3D memory array with read bit line shielding | Electricity | 5 | Active |
| US8976604B2 | Method and apparatus for copying data with a memory array having redundant memory | Physics | 5 | Active |
| US8976600B2 | Word line driver circuit for selecting and deselecting word lines | Physics | 4 | Active |
| US8638618B2 | Decoder for NAND memory | Physics | 4 | Active |
| US6411120B1 | Output buffer drive circuit with initial drive for semiconductor devices | Electricity | 4 | Expired |
| US8527839B2 | On-the-fly repair method for memory | Physics | 3 | Active |
| US8149624B1 | Method and apparatus for reducing read disturb in memory | Physics | 3 | Active |
| US8542532B2 | Memory access method and flash memory using the same | Physics | 3 | Active |
| US11049585B1 | On chip block repair scheme | Physics | 3 | Active |
| US9773571B2 | Memory repair redundancy with array cache redundancy | Physics | 2 | Active |
| US8982622B2 | 3D memory array with read bit line shielding | Electricity | 2 | Active |
| US6930926B2 | Method for erasing a flash EEPROM | Physics | 2 | Expired |
| US11048649B2 | Non-sequential page continuous read | Physics | 2 | Active |
| US10290364B2 | Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks | Physics | 1 | Active |
| US8665646B2 | Method and apparatus for indicating bad memory areas | Physics | 1 | Active |
| US9805803B2 | Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage | Physics | 1 | Active |
| US11249913B2 | Continuous read with multiple read commands | Physics | 1 | Active |
| US8947961B2 | Management of non-volatile memory | Physics | 1 | Active |
| US8526235B2 | Method and apparatus for reducing read disturb in memory | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.