Self-aligned interconnection for integrated circuits
US11049769B2 · kind B2 · utility
0Cited by
17References
19Claims
0Family size
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Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Aug 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.