Semiconductor wafer having trenches with varied dimensions for multi-chip modules
US11049844B2 · kind B2 · utility
1Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Jul 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/367
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.