Semiconductor device for preventing defects between bit lines and channels
US11049847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Jan 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first semiconductor structure comprising a substrate and a circuit element, and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes a base layer, a first memory cell structure, a second memory cell structure, and common bit lines between the first memory cell structure and the second memory cell structure. The first memory cell structure includes first gate electrodes, first channel structures, and first string select channel structures. The second memory cell structure includes second gate electrodes, second channel structures, second string select channel structures, and connection regions between the second channel structures and the second string select channel structures. The first memory cell structure further includes first channel pads between the common bit lines and the first string select channel structures, and the second memory cell structure further includes second channel pads extending along the common bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.