Test circuits for testing a die stack

US11054461B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Nui Chong · San Jose, US
• Amitava Majumdar · Boise, US
• Cheang-Whang Chang · Mountain View, US
• Henley Liu · San Jose, US
• Myongseob Kim · Pleasanton, US
• Albert Shih-Huai Lin · Mountain View, US

Key dates

• Filing date: Mar 12, 2019
• Grant date: Jul 6, 2021
• Expiry date: May 10, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06596
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.