Patent · US Active

Multi-port memory circuitry

US11056183B2 · kind B2 · utility

1Cited by

0References

14Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Yew Keong Chong · Austin, US
Andy Wangkun Chen · Austin, US
Sriram Thyagarajan · Austin, US

Key dates

Filing date	Apr 24, 2018
Grant date	Jul 6, 2021
Priority date	—
Expiry date	Apr 24, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10B10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.