Wafer processing method
US11056346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68327
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a wafer processing method for reducing a thickness of a wafer. The wafer has a front side and a back side opposite to the front side. The wafer has a device area where a plurality of devices are formed on the front side and a peripheral marginal area including a curved peripheral edge. A protective layer for covering the plural devices are formed on the front side in the device area. The wafer processing method includes a plasma etching step of supplying an etching gas in a plasma condition to the front side of the wafer by using the protective layer as a mask, thereby removing the peripheral marginal area including the curved peripheral edge, a protective member attaching step of attaching a protective member to the front side of the wafer, and a grinding step of grinding the back side of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.