Forming array contacts in semiconductor memories
US11056383B2 · kind B2 · utility
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5References
14Claims
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Assignee
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Key dates
| Filing date | Jan 26, 2018 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Feb 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.