Method of manufacturing semiconductor package using alignment mark on wafer
US11056410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2018 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.