Three-dimensional NAND memory device with source line comprising metallic and semiconductor layers
US11056501B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Aug 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a memory device comprises a conductive layer containing a metal, a semiconductor layer on the conductive layer, electrode layers stacked on the semiconductor layer in a stacking direction, a semiconductor pillar penetrating the electrode layers in the stacking direction and electrically connected to the semiconductor layer, and a charge trap layer between the electrode layers and the semiconductor pillar. The conductive layer has a recess or a through-hole below the semiconductor pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.