Patent · US Active

Data selection network for a data processing engine in an integrated circuit

US11061673B1 · kind B1 · utility

0Cited by

36References

16Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Baris Ozgul · Dublin, IE
Jan Langer · Chemnitz, DE
Juan J. Noguera Serra · San Jose, US
Goran H K Bilski · Mölndal, SE
Richard L. Walke · Edinburgh, GB

Key dates

Filing date	Apr 3, 2018
Grant date	Jul 13, 2021
Priority date	—
Expiry date	Aug 15, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F17/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.