Virtual cache mechanism for program break point register exception handling
US11061810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Feb 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of stopping program execution includes tagging an entry in a virtual cache with an indicator bit where the virtual address of the entry corresponds to a virtual address range in a break point register, in response to a second virtual cache data access demand matching the entry tagged with the indicator bit, determining whether the second data access demand matches the virtual address range of the breakpoint register, and in response to the second data access demand matching the virtual address range of the break point register, flagging an exception and stopping execution of the program. In an embodiment, the method or system enters a slow-mode in response to the second data access demand matching the virtual cache entry with the indicator bit, and performs a full comparison between the second data access demand and the break point register virtual address range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.