Three-dimensional memory device programming with reduced disturbance
US11062782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Nov 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory decks each including a plurality of memory layers in a vertical direction, and a plurality of first dummy memory layers between the first and second memory decks in the vertical direction. Each memory layer in a first memory deck of the plurality of memory decks is first programmed. The first programming includes applying a program voltage to the memory layer and a channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck. Each memory layer in a second memory deck of the plurality of memory decks above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the channel pass voltage to each of the rest of the memory layers in the second memory deck. The second programming also includes applying a 0 V-voltage to at least one of the first dummy memory layers. The second programming further includes applying the 0 V-voltage to each memory…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.