Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer

US11063208B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Jun Chen · Hubei, CN
• Hung Cho Wang · Taipei, TW

Key dates

• Filing date: Nov 1, 2019
• Grant date: Jul 13, 2021
• Expiry date: Nov 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/85

Abstract

An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.