HEMT wafer probe current collapse screening
US11067620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2642
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.