Test line letter for embedded non-volatile memory technology
US11069419B2 · kind B2 · utility
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8References
20Claims
0Family size
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Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Nov 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.