Patent · US Active

Phase controlled codec block scan of a partitioned circuit device

US11073557B2 · kind B2 · utility

2Cited by
11References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 8, 2019
Grant dateJul 27, 2021
Priority date
Expiry dateJun 16, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318575
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.