Methods for error count reporting with scaled error count information, and memory devices employing the same
US11074126B2 · kind B2 · utility
5Cited by
1References
20Claims
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Key dates
| Filing date | Jul 11, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Jul 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.