IC having trench-based metal-insulator-metal capacitor

US11075157B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Mona Eissa · Plano, US
• Umamaheswari Aghoram · Richardson, US
• Pushpa Mahalingam · Richardson, US
• Erich Wesley Kinder · Notre Dame, US
• Bhaskar Srinivasan · Boise, US
• Brian E. Goodlin · Plano, US

Key dates

• Filing date: Sep 9, 2019
• Grant date: Jul 27, 2021
• Expiry date: Sep 9, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.