Large via buffer
US11075161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Jun 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure is provided. The interconnect structure includes a first metallization layer, an insulating layer and a second metallization layer. The first metallization layer includes, at an uppermost surface thereof, a first body formed of first dielectric material, first metallic elements and buffer elements formed of second dielectric material adjacent the first metallic elements. The insulating layer is disposed on the uppermost surface of the first metallization layer and defines apertures located at the first metallic elements and the corresponding buffer elements. The second metallization layer is disposed on the insulating layer and includes a second body formed of first dielectric material and second metallic elements located at the apertures and extending through the apertures to contact the corresponding first metallic elements and the corresponding buffer elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.