Memory arrays and methods used in forming a memory array
US11075215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2020 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | May 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.