Software-invisible interrupt for a microprocessor
US11080122B2 · kind B2 · utility
0Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Dec 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.