Addressing scheme for a memory system
US11080219B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jan 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.