Eric J. Stave
46Patents
8h-index
30Co-inventors
75Inventor score
Filing activity: Feb 12, 1997 → Jan 3, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5734198A | Multi-layer lead frame for a semiconductor device | Electricity | 44 | Expired |
| US6438043B2 | Adjustable I/O timing from externally applied voltage | Physics | 39 | Expired |
| US6002623A | Semiconductor memory with test circuit | Physics | 23 | Expired |
| US5684809A | Semiconductor memory with test circuit | Physics | 19 | Expired |
| US6154078A | Semiconductor buffer circuit with a transition delay circuit | Electricity | 13 | Expired |
| US6166576A | Method and apparatus for controlling timing of digital components | Electricity | 12 | Expired |
| US6307255A | Multi-layer lead frame for a semiconductor device | Electricity | 9 | Expired |
| US6515353B2 | Multi-layer lead frame for a semiconductor device | Electricity | 8 | Expired |
| US6124630A | Multi-layer lead frame for a semiconductor device | Electricity | 7 | Expired |
| US5892720A | Semiconductor memory with test circuit | Physics | 6 | Expired |
| US6278310A | Semiconductor buffer circuit with a transition delay circuit | Electricity | 4 | Expired |
| US6788126B2 | Semiconductor buffer circuit with a transition delay circuit | Electricity | 4 | Expired |
| US10424356B2 | Methods for on-die memory termination and memory devices and systems employing the same | Physics | 4 | Active |
| US7574634B2 | Real time testing using on die termination (ODT) circuit | Physics | 3 | Expired |
| US5965936A | Multi-layer lead frame for a semiconductor device | Electricity | 3 | Expired |
| US6707312B2 | Pseudo variable resistor for tester platform | Electricity | 2 | Expired |
| US7664999B2 | Real time testing using on die termination (ODT) circuit | Physics | 2 | Active |
| US11416437B2 | Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities | Physics | 2 | Active |
| US7167401B2 | Low power chip select (CS) latency option | Physics | 2 | Expired |
| US7274606B2 | Low power chip select (CS) latency option | Physics | 2 | Active |
| US11217284B2 | Memory with per pin input/output termination and driver impedance calibration | Physics | 1 | Active |
| US6515529B2 | Semiconductor buffer circuit with a transition delay circuit | Electricity | 1 | Expired |
| US11545199B2 | Methods for on-die memory termination and memory devices and systems employing the same | Physics | 1 | Active |
| US11031070B1 | Apparatus and method for performing continuous time linear equalization on a command/address signal | Physics | 1 | Active |
| US11080219B1 | Addressing scheme for a memory system | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.