Memory device random option inversion
US11081166B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.