Sense amplifier architecture for low supply voltage operations
US11081167B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jun 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.