Patent · US Active

Die stack with reduced warpage

US11081451B2 · kind B2 · utility

1Cited by

1References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Yong She · Shanghai, CN
Bin Liu · Fishers, US
Zhicheng Ding · Shanghai, CN
Aiping Tan · Shanghai, CN

Key dates

Filing date	Mar 10, 2017
Grant date	Aug 3, 2021
Priority date	—
Expiry date	Mar 10, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.