Aiping Tan
9Patents
1h-index
4Co-inventors
36Inventor score
Filing activity: Sep 29, 2016 → Aug 2, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10770434B2 | Stair-stacked dice device in a system in package, and methods of making same | Electricity | 2 | Active |
| US10727208B2 | Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same | Electricity | 1 | Active |
| US11081451B2 | Die stack with reduced warpage | Electricity | 1 | Active |
| US10971478B2 | Interposer design in package structures for wire bonding applications | Electricity | 0 | Active |
| US10930622B2 | Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same | Electricity | 0 | Active |
| US10991679B2 | Stair-stacked dice device in a system in package, and methods of making same | Electricity | 0 | Active |
| US11652087B2 | Interposer design in package structures for wire bonding applications | Electricity | 0 | Active |
| US11848281B2 | Die stack with reduced warpage | Electricity | 0 | Active |
| US11538746B2 | Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.