FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US11081583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Oct 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.