Mapping consecutive logical block addresses to consecutive good blocks in memory device
US11086539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2019 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.