Loc Tu
21Patents
10h-index
23Co-inventors
75Inventor score
Filing activity: Dec 12, 2002 → Mar 31, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7099194B2 | Error recovery for nonvolatile memory | Physics | 129 | Expired |
| US6829167B2 | Error recovery for nonvolatile memory | Physics | 126 | Expired |
| US7457178B2 | Trimming of analog voltages in flash memory devices | Physics | 45 | Active |
| US7254071B2 | Flash memory devices with trimmed analog voltages | Physics | 37 | Expired |
| US7477545B2 | Systems for programmable chip enable and chip address in semiconductor memory | Physics | 24 | Active |
| US7715255B2 | Programmable chip enable and chip address in semiconductor memory | Electricity | 23 | Active |
| US7453731B2 | Method for non-volatile memory with linear estimation of initial programming voltage | Physics | 23 | Active |
| US8018769B2 | Non-volatile memory with linear estimation of initial programming voltage | Physics | 12 | Active |
| US7599223B2 | Non-volatile memory with linear estimation of initial programming voltage | Physics | 11 | Active |
| US7606091B2 | Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage | Physics | 10 | Active |
| US8446772B2 | Memory die self-disable if programmable element is not trusted | Emerging Cross-Sectional Technologies | 9 | Active |
| US8826086B2 | Memory card test interface | Physics | 9 | Active |
| US7606077B2 | Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage | Physics | 7 | Active |
| US7561482B2 | Defective block isolation in a non-volatile memory system | Physics | 4 | Active |
| US9218895B2 | Memory card test interface | Physics | 1 | Active |
| US11687252B2 | Non-volatile memory with pre-trained model and inference circuit | Electricity | 0 | Active |
| US11372056B2 | Circuit for detecting pin-to-pin leaks of an integrated circuit package | Physics | 0 | Active |
| US11086539B2 | Mapping consecutive logical block addresses to consecutive good blocks in memory device | Physics | 0 | Active |
| US12099743B2 | Non-volatile memory integrated with artificial intelligence system for preemptive block management | Physics | 0 | Active |
| US10984883B1 | Systems and methods for capacity management of a memory system | Physics | 0 | Active |
| US11756630B2 | Obtaining threshold voltage measurements for memory cells based on a user read mode | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.