Sense amplifier architecture providing small swing voltage sensing
US11087800B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Apr 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier architecture is presented that can reduce sensing times by being able to sense smaller voltage swings between an ON memory cell and an OFF memory cell. The sense amplifier includes a sensing capacitor that, on one side, is connectable to multiple bit lines and, on the other side, to a main sense amplifier section. The main section includes a latch formed of a pair of inverters that has an input connected to the capacitor and an output that is connected to the other side of the capacitor by a third inverter. To pre-charge the latch, the input and output nodes are shorted and then the capacitor is connected to discharge the capacitor through a selected memory cell based on whether it is ON or OFF. A programming data latch for each bit line can bias the bit line to either a program enable or program inhibit level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.