Edge memory array mats with sense amplifiers
US11087827B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.