Memory system with single decoder, multiple memory sets and method for decoding multiple codewords from memory sets using the single decoder
US11087846B1 · kind B1 · utility
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6References
16Claims
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Key dates
| Filing date | Feb 12, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 12, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including memory sets and a controller including a decoder. The decoder receives multiple codewords from the memory sets and decodes the multiple codewords. The decoder determines an inter-set delay for a codeword of a select memory set. When the inter-set delay is greater than a maximum inter-set delay, the decoder determines a total decoding time based on an effective inter-set delay and an effective decoding time. The decoder outputs the decoded codeword at the end of the total decoding time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.