Non-volatile memory with bit line controlled multi-plane mixed sub-block programming
US11087849B2 · kind B2 · utility
9Cited by
7References
11Claims
0Family size
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Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.