Inventor · San Jose, CA, US

Zhenming Zhou

138Patents
9h-index
66Co-inventors
79Inventor score

Filing activity: Feb 7, 2013 → May 14, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9036417B2 On chip dynamic read level scan and error detection for nonvolatile storage Physics 26 Active
US9460799B1 Recovery of partially programmed block in non-volatile memory Physics 23 Active
US9548124B1 Word line dependent programming in a memory device Physics 16 Active
US9563504B2 Partial block erase for data refreshing and open-block programming Electricity 15 Active
US9530517B2 Read disturb detection in open blocks Physics 15 Active
US10950315B1 Preread and read threshold voltage optimization Physics 14 Active
US10636498B1 Managing bit-line settling time in non-volatile memory Electricity 13 Active
US9805809B1 State-dependent read compensation Physics 12 Active
US11087849B2 Non-volatile memory with bit line controlled multi-plane mixed sub-block programming Physics 9 Active
US8861269B2 Internal data load for non-volatile storage Physics 9 Active
US10790036B1 Adjustment of read and write voltages using a space between threshold voltage distributions Physics 8 Active
US9564226B1 Smart verify for programming non-volatile memory Physics 8 Active
US9710325B2 On chip dynamic read level scan and error detection for nonvolatile storage Physics 8 Active
US9047974B2 Erased state reading Physics 6 Active
US9530504B2 Memory cells using multi-pass programming Physics 5 Active
US11101001B2 Non-volatile memory with multi-plane mixed sub-block programming Physics 5 Active
US10908845B1 Managing threshold voltage drift based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system Physics 3 Active
US11768615B1 Temperature-based media management for memory components Physics 2 Active
US11495316B1 Optimized seasoning trim values based on form factors in memory sub-system manufacturing Physics 2 Active
US9053820B2 Internal data load for non-volatile storage Physics 2 Active
US10726925B2 Manage source line bias to account for non-uniform resistance of memory cell source lines Electricity 2 Active
US11742029B2 Adjusting read-level thresholds based on write-to-write delay Physics 1 Active
US12014049B2 Adaptive sensing time for memory operations Physics 1 Active
US11526295B2 Managing an adjustable write-to-read delay of a memory sub-system Physics 1 Active
US11244740B1 Adapting an error recovery process in a memory sub-system Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.