Structure and formation method of interconnection structure of semiconductor device
US11088020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2017 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Aug 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53242
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.