Metal block and bond pad structure
US11088192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Dec 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48451
Abstract
In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.