Memory device with dynamic cache management
US11093385B2 · kind B2 · utility
2Cited by
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24Claims
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Key dates
| Filing date | Nov 27, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Nov 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.