Concurrent read and reconfigured write operations in a memory device
US11094375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Mar 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.