In-memory compute array with integrated bias elements
US11094376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | May 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.