Doped and undoped vanadium oxides for low-k spacer applications
US11094533B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Oct 2, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Oct 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.