Patent · US Active

Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers

US11094637B2 · kind B2 · utility

14Cited by

20References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Joshua M. Rubin · Albany, US
Steven L. Wright · Whitehall Corners, US
Lawrence A. Clevenger · Saratoga Springs, US

Key dates

Filing date	Nov 6, 2019
Grant date	Aug 17, 2021
Priority date	—
Expiry date	Nov 6, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.