Three-dimensional memory devices and fabricating methods thereof

US11094714B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Liang Chen · 红钢城街道, CN
• Lei Xue · 红钢城街道, CN
• Wei Liu · 红钢城街道, CN
• Shi Qi Huang · Hubei, CN

Key dates

• Filing date: Dec 30, 2019
• Grant date: Aug 17, 2021
• Expiry date: Dec 30, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06541
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.