Multi-stage bit line pre-charge
US11100964B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.