Gap fill deposition process
US11101174B2 · kind B2 · utility
14Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Oct 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming an interconnections structure on a substrate in a cluster processing system and thermal processing such interconnections structure are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap filling layer on the interface layer, and performing an annealing process on the substrate, wherein the annealing process is performed at a pressure range greater than 5 bar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.