Field-effect transistors with diffusion blocking spacer sections
US11101364B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Apr 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.