Patent · US Active

Circuit arrangements and methods for traversing input feature maps

US11106968B1 · kind B1 · utility

3Cited by

2References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Ehsan Ghasemi · San Jose, US
Elliott Delaye · San Jose, US
Ashish Sirasao · San Jose, US

Key dates

Filing date	May 24, 2018
Grant date	Aug 31, 2021
Priority date	—
Expiry date	Feb 28, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06N3/0464
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit arrangement includes a buffer, a height traversal circuit configured to generate a sequence of IFM height values in response to first control signals, a width traversal circuit configured to generate a sequence of IFM width values in response to second control signals, a control circuit, and an address generation circuit. The control circuit is configured to input an OFM height, an OFM width, a kernel height, and a kernel width; generate the first control signals at times based on the OFM height and the kernel height; and generate the second control signals at times based on the OFM width and the kernel width. The address generation circuit is configured to generate a sequence of addresses based on the sequences of IFM height values and IFM width values, provide the sequence of addresses to the buffer, and enable reading from the buffer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.